1. Field of the Invention
This invention relates to processors and, more particularly, to implementation of shared resources in processors having multiple cores.
2. Description of the Related Art
To improve execution performance, processors commonly include multiple levels of caches. For example, a processor may include a fast first-level (L1) cache backed by a larger, slower second-level (L2) cache. Such an arrangement may reduce average memory access latency relative to an implementation in which the L2 cache is omitted, in that an L1 cache miss that hits in the L2 cache need not incur the full latency of an access to system memory.
The integration of multiple processor cores into a single processor (also referred to as a multicore processor) has resulted in configurations in which several independent L1 caches within the cores may share a common L2 cache. For example, in an 8-core processor, individual instruction and data caches within each of the 8 cores may share access to a larger L2 cache integrated within the processor, such that upon a cache miss, any of the L1 caches may receive data from the L2 cache.
Generally speaking, the performance of a multicore processor may increase when the number of cores and/or cache size is increased. For example, increasing the number of cores generally increases the resources available to perform concurrent operations, allowing more computational work to be done in a given amount of time. Increasing a cache's size generally decreases the cache's miss rate, which decreases average memory access latency and thus reduces the amount of time a computational task must wait for data and/or instructions to become available for use.
However, increasing the number of cores and/or cache size may substantially increase the implementation complexity of a multicore processor. For example, doubling the number of cores may double the number of wires needed to provide data to the cores from the L2 cache. Such increases in wire counts may lead to routing and floorplanning difficulties as well as increased power consumption, among other costs. Although improvements in process technology may provide some relief, the implementation costs of scaling a multicore design may quickly become nonlinear, and linear scaling techniques (such as simply scaling resources and interconnect by the same factor) may prove infeasible or impractical.